This project seeks to develop a multichannel readout ASIC with each channel incorporating a fast front-end and timestamping (using a Time to Digital converter or TDC) with a time bin of 20 ps. It builds on experience already gained with the FastIC, an 8 channel ASIC designed between CERN and University of Barcelona with the support of the KT fund. FastIC only contains the front-end circuits; the addition of a TDC per channel enables compact system integration and low power consumption.